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| i advance information i i real-time clock plus ram (rtc) the MC146818A real-time clock plus ram is a peripheral device which includes the unique motel concept for use with various microprocessors, microcomputers, and larger computers. this part combines three unique features: a complete time-of-day clock with alarm and one hundred year calendar, a programmable periodic inter- rupt and square-wave generator, and 50 bytes of low-power static ram. the MC146818A uses high-speed cmos technology to interface with 1 mhz processor buses, while consuming very little power. the real-time clock plus ram has two distinct uses. first, it is designed as a battery powered cmos part (in an otherwise nmos/ttl system) including all the common battery backed-up functions such as ram, time, and calendar. secondly, the MC146818A maybe used with a cmos microprocessor to relieve the software of the timekeeping ,~~ workload and to extend the available ram of an mpu such as the ., ??~:$ mc146805e2. ,!!:\?; .\,i,. , .. . . . . . l low-power, high-speed cmos ~ \}t ,.,.>*t!f\+ {k ,1, $s,,.. l internal time base and oscillator ~;, ~p )>. ~$$~. ?,& q.%~!* o counts seconds, minutes, and hours of the day *>sq,.,,\ ,$4:*, $+.~:;;, . ..~. ??t:>?,. l counts days of the week, date, month, and year ,$: ;<4 , l 3 v to 6 v operation . .! .*:,: ~t.k ,$,., l time base input options: 4.194304 mhz, 1.048ti ~~z, or 32.7w khz ,, ,,,,m, ,)$ f, <..%.- . . . *<.*$, ,$\ \., ,,:,, . ..i,;t~ l time base oscillator for parallel resonan~$$~{s]s .~;\l.. . l 40 to 200 pw typical operating power{,~l:~#~ ?frequency time base l 4.0 to 20 mw typical operating po.~%j~*$?gh frequency time base ,~$.~,,, l binary or bcd representation ~ftw~ calendar, and alarm l 12- or 24-hour clock with a~$oq$pm in 12-hour mode .$k, ..?.l ,{+<, ,$$,> :,., l daylight savings time oplwn ?$ *;* $*,, $$ l automatic end of mo~:~??~$e6gnition l automatic leap y~r ~&&~ensation l microprocessor#$@t@mpatible ~ ?. $$ *$ l selectable ba$w&n?wotorola and competitor bus timing , - ~.,y, }$~* l multiplex@:~@ fbr pin efficiency ~?.,-,, l lnterfq&$&%@% software as 64 ram locations l 14 b~es:$?~ciock and control registers ,,*j l ~?~~~~$i?of general purpose ram . . . . ~. @x;.$j&%ws bit indicates data integrity ?{&us compatible interrupt signals (~q) . . l three interrupts are separately software maskable and testable time-of-day alarm, once-per-second to once-per-day periodic rates from 30.5 ps to 500 ms end-of-clock update cycle l programmable square-wave output signal l clock output may be used as microprocessor clock input at time base frequency -1 or +4 l 24-pin dual-in-line package l quad pack also available . hls document contains !ntormatlon on a new product. specltlcatlons and tntormatlon here!n MC146818A cmos \ case 623 u? i pin assignment ?ot ~vdd oscl [ 2 23 ] sqw 0sc2 [ 3 22 ] ps ado [ 4 21 jckout ad1 [ 5 20 ] ckfs ad2 [ 6 lg ] l~q ad3 [ 7 18 ] reset ad4 [ 8 17 ] ds ad5 c g 16 ] stby ad6 [ 10 15 ] rl~ ad7 [ 11 14 ] as vss [ 12 13 ]= )motorolainc,, lw adi-1026 are subject to change without notice
figure 1 ? block diagram clock ~ ckout + output ~ ckfs v storage temperature range tstg ?55to +150 oc thermal characteristics characteristic symbol i value unit user ram (50 bytes) sow ~q reset ps ,i,>,~ . . ~><., ,* .*$:, \ h . ~ :*. . . . ?+ $.;).,,< ,:? ,?<;}.: - maximum ratinq~~(@ojjages referenced to vss) r~$n& ?~:?? symbol value unit supply volta~j** ? ?$? vdd ?0.3 to +8.0 v all input v:$~&.~xcept osc1 vin v5s? o.5 to vdd+o.5 v current ~rai~~r pin excluding vmi,a%q,.vs s i 10 ma this device contains circuitry to protect the in- op&~~~&temperature range puts against damage due to high static voltages tl to th or electric fields; however, it is advised that nor- ?~%$~6818a 0 to 70 ?<@c146818ac mal precautions be taken to avoid application of ta ? 40 to 85 oc any voltage higher than maximum rated voltages to this high-impedance circuit. for proper opera- tion it is recommended that vin and vout be con- strained to the range vss =(vin or voutl s vdd. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e. g., either vss or vdd). thermal resistance plastic i i 120 i i cerdlp 9ja 65 ?c/w ceramic 50 @ motorola semiconductor products inc. 2 ? ? )c electrical characteristics (vd d = 3 vdc, vs s = o vdc, ta = tl to th unless otherwise noted) characteristics i symbol i min i max i unit i frequency of operation fosc 32.768 32.768 khz output voltage vol ? 0.1 lload< lopa voh v vdd? o.1 ? idd ? bus idle ckout=fosc, cl= 15 pf; sow disabled, stby=o.2 v; cl (osc2)= 10 pf fosc=32.76b khz .\, idd3 ? 50 a&fi%$k idd ? quiescent idd4 ? 50 ?~ {?. fosc= dc; osc1 = dc; $??:#$, !, ~~.+ ,, ~ i:? all other lnputs=vdd?0.2 v; :,.: ,.~ ~+ ,, . . . . . .:s. ? .. no clock i,,.. ..,t>.$. ? :.*$ \k;~# \ ~, . ...,. output high voltege .,+ ..% )$ i?t? * (l load= ? 0.25 ma, all outputs) ~-.>,,->, ,.,/, voh 2.7 t +??+?~??t;;k~ v output low voltage ?j figure 3 ? bus read timing competitor multiplexed bus ?le(addresslatch ~ (read output enable) (ds pin) i il c= (chip select) stby ado-ad7 (address/ data bus) figure 4 ? bus write timinti?@petitor multiplexed bus @- *w 25 . 31 < ; ?- j a @ ado-ad7 (address/ data bus) address write data valid valld note: vhigh=vdd-2.o v, vlow=o.8 v, for vdd=5.o v a 10% for outputs only. vhigh=2.o v, vlow=o.5 v, for vdd=3.o v for outputs only. @ motorola semiconductor products inc. 5 table 1 ? switching characteristics (vss=o vdc, ta= tl to th) vdd=3.o vdc vdd = 5.0 vdc & 10?a i description i symbol i min i max i unit i min i max i unit i oscillator startu~ ltrrl? ltbdlms]? ll~lmsl 1 reset pulse width i trwl [ tbd i ? i ks i 51? i ps i reset delay time trlh i tbd i ? i ps i 51? &s da,.,-. c---- d, ,1-- !ai; a+l i +-, .,, tdn i ..- c i i ?i\! ds reset itq . all outputs except osc2 (see figure 10) 2k mm d7000 or equivalent . vdd (kq oniv) t l 130pf m motorola semiconductor products inc. 6 -. .? .? ? vdd pin reset pin ckout pin vdd pin ov ps pin . ov figure 7 ? power-up ~~ ~ the vrt bit is set to a ,1?, by reading register d. the vrt bit mn only be cleared by pulling the ps pin low (see register d ($od)). @ motorola semiconductor products inc. 7 signal descriptions the block diagram in figure 1, shows the pin connection with the major internal functions of the MC146818A real- time clock plus ram. the following paragraphs describe the function of each pin. vdd, vss dc power is provided to the part on these two pins, vdd being the more positive voltage. the minimum and maxi- mum voltages are listed in the electrical characteristics tables. mot?motel the mot pin offers flexibility when choosing bus type, when tied to vdd, motorola timing is used. when tied to vss, competitor timing is used. the mot pin must be hard- wired to the vdd or vss supply and cannot be switched during operation of the MC146818A. osc1, osc2 ? time base, inputs the time base for the time functions may be an external signal or the crystal oscillator. external square waves at 4.184304 mhz, 1.m576 mhz, or 32.768 khz may be con- nected to osci as shown in figure 9. the internal time-base frequency to be used is chosen in register a. the on-chip oscillator is designed for a parallel resonant at cut crystal at4.1 m04 mhz, 1.048576 mhz or32.768 khz frequencies. the crystal connections are shown in figure 10 and the crystal characteristics in figure 11. ckout ? clock out, output the ckout pin is an output at the time-base freque~~ divided by 1 or 4. a major use for ckout is as the t~u~:t, clock to the microprocessor; thereby saving the c,@$:&::@ second crystal. the frequency of ckout depends%~okt$he ..j:. + .k?~ ckfs ? clock out frequency #%&<$: input when the ckfs pin is tied to vd~$~$:jcai~es ckout to be the same frequency as the time b~e ~~fie osci pin. when ckfs is tied to vss, ckouj:~~l~@~oscl time-base fre- quency divided by four. t~le~~ summarizes the effect ,,: ., ,, ~me base,, ~~~ ~=~k frequency ( oscl~, ;$t~,; ?+ select hn freq~ ~,,,,, ?? (ckfs) 4.ly3~,,myz high ,., ..r ? 4.w: m hz low ~$+&6 mhz high ?:\:~576 m hz low ?32.768 khz high 32.7& khz low sqw ? square wave, output clock frequency output hn (ckout) 4.1943w mhz 1.w576 mhz 1.w576 mhz 262.144 khz 32.768 khz 8.192 khz the sqw din can output a signal from one of the 15 taps provided by ihe 22 internal-divid~r stages. the frequency of the sqw may be altered by programming register a, as shown in table 5. the sqw signal may be turned on and off using the sqwe bit in register b. ado-ad7 ? multiplexed bidirectional addressidata bus multiplexed bus processors save pins by presenting the address during the first portion of the bus cycle and using the same pins during the second portion for data. address- then-data multiplexing does not slow the access time of the MC146818A since the bus reversal from address to data is occurring during the internal ram access time. \\;~,;. >.t,, . . . . ,..,$) . the address must be valid just prior to the fall ,@#~$~~le at which time the m c146818a latches the addr.e~ ??@ ado to ad5, valid write data must be presente@t~~~~fi8?d stable during the latter portion of the ds or ~~~~?~~. in a read cycle, the m c146818a outputs eight ~[~bf~~ta during the latter portion of the ds or ~ pulse~$~$~mases driving the bus (returns the output drivers to t~,h,$h-impedance state) when ds falls in the motorola&cj&e o~~otel or r~ rises in the other case. ..,~t;~, .?)? as ? multiplex~:~@#~ss strobe, input +,tp:=,y,t\> a positive goin~+ mu~~[pjexed address strobe pulse serves to demultiplex t~~x,~~s. the falling edge of as or ale causes the address+~:$~~atched within the MC146818A. \ ., ,!:!~ ?,$$v<,,:hi:. ds ~ #&$a??strobe or read, input ~~,ds pin has two interpretations via the motel circuit, ,:&$$n@manating from a motorola type processor, ds is a .,,, %~o$$lve pulse during the latter portion of the bus cycle, and !,, . , *~~&$ariously called ds (data strobe), e (enable), and 42 (42 ..-,:::.j+>, 4.1%304 mhz or 1.w576 mhz 32.7:; khz figure 9 ? external time-base connection $ vdd optional (vdd?1.o vi i i 2 3 (open)MC146818A ,.. ,!~.- osc2 MC146818A fow 4.1- mhz 1.046576 mhz 32.7@ khz rs (maximum) 75 q 700 n wk co (maximum) 7 pf 5 pf 1.7 pf cl 0.012 pf 0.~8 pf 0.~3 pf q 50 k 35 k 30 k cin/cout 15-30 pf 15-40 pf 10-22 pf r ? ? 300-470 k rf 10 m 10 m 22 m @ motorola semiconductor products inc. 9 ~q? interrupt request, output the irq pin is an active low output of the mc14w18a that may be used as an interrupt input to a processor, the ~q output remains low as long as the status bit causing the in- terrupt is present and the corresponding interrupt-enable bit is set. to clear the 1~ pin, the processor program normally reads register c. the reset pin also clears pending inter- rupts. when no interrupt conditions are present, the ~q level is in the high-impedance state. multiple interrupting devices may thus be connected to an ~q bus with one pullup at the processor. reset ? reset, input the reset pin does not affect the clock, calendar, or ram functions. on powerup, the reset pin must be held low for the specified time, trlh, in order to allow the power supply to stabilize. figure 12 shows a typical representation of the reset pin circuit. when reset is low the following occurs: a) periodic interrupt enable (pie) bit is cleared to zero, b) alarm interrupt enable (aie) bit is cleared to zero, c) alarm interrupt enable (aie) bit is cleared to zero, d) update ended interrupt flag (uf) bit is cleared to zero, e) interrupt request status flag (irqf) bit is cleared to zero, f) periodic interrupt flag ( pf) bit is cleared to zero, g) the part is not accessible. h) alarm interrupt flag (af) bit is cleared to zero, i) irq pin is in high-impedance state, and j) square wave output enable (sqwe) bit is cleared jq zero, . . . ? ~l~\ stby ? stand? by tfi?>\t:;*g*\\$ .,. ?~?+! ,,,:*.lf, ,, .,,,.$ the stby pin, when active, prevents ac~s~$~ ?the MC146818A making it ideal for battery back-~?~~~l~ations. stand-by operation incorporates a transpa~~$$~~$tch, after data strobe (ds) goes low (td or _j:rn@), stby is .:>.$,:< recognized as a valid signal. j*! $$3, n the stby signal is totally asyr*l@6s. its transpare~t latch is opened by the falling e~~~.of .@s (rising edge of rd ~.$, *,% 2?$\$- or ~r) and clocked by the r$@n@~dge of as (ale). there- fore, for stby to be reco$oize@t@s and as should occur in pairs. when stby gop@~l,w,,before the falling edge of ds (rising edge of ~r ?r ~~k$~re current cycle is completed at that edge and thq $h<,~ycle will not be executsd. \ ~.. .!,... s*, \?~*~> ps ? pow,~?:j~~$e, input the pq,v&-s~$se pin is used in the control of the valid ram @~~~$ (vrt) bit in register d. when the ps pin is low ~@q,w~~t bit is cleared to zero. w~@?using the vrt feature during powerup, the ps pin must % externally held low for the specified tplh time. as power is applied, the vrt bit remains low indicating that the contents of the ram, time registers, and calendar are not guaranteed. ps must go high after powerup to allow the vrt bit to be set by a read of register d, figure 12?typical powerup delay circuit for reset di d2 .,~!,:~,,+ . . not~~${,the rtc is isolated from the mpu or m cu power by a ,~j,,,t dwe drop, care must be taken to meet vin requirements. ~y 1~~ ,,f:~ figure 13 ? typical powerup delay circuit for power sense di d2 i vdd ps mc146818 vss t + 2.0 k i 0.005 ~f di = m bd701 (schottky) or equivalent d2 = 1 n4148 or equivalent m motorola semiconductor products inc. 10 power-down considerations in most systems, the MC146818A must continue to keep time when system power is removed. in such systems, a conversion from system power to an alternate power supply, usually a battery, must be made. during the transition from system to battery power, the designer of a battery backed-up rtc system must protect data integrity, minimize power consumption, and ensure hardware reliability. the stand-by (stby) pin controls all bus inputs (r/~, ds, as, ado-ad7) st by, when negated, disallows any unintended modification of the rtc data by the bus. stby also reduces power consumption by reducing the number of transitions seen internally. power consumption may be further reduced by removing resistive and capacitive loads from the clock out (ckout) pin and the squarewave (sqw) pin. during and after the power source conversion, the vin maximum specification must never be exceeded. failure to meet the vin maximum specification can cause a virtual scr to appear which may result in excessive current drain and destruction of the part. address map figure 14 shows the address map of the MC146818A, the memory consists of 50 general purpose ram bytes, 10 ram bytes which normally contain the time, calendar, and alarm data, and four control and status bytes, all 64 bytes are directly readable and writable by the processor program ex- cept for the following: 1 ) registers c and d are read only, 2) bit 7 of register a is read only, and 3) the high-order bit of the seconds byte is read only. the contents of four control and status registers (a, b, c, and d) are described in registers. .fi.?.? ,~.. ,.,., ~? ~:, .:$.., ?%<. ?,+ time, calendar, and alarm locations . . ..?t)\..).$ table 3 ? time, calendar, and alarm data modes address decimal range example? location function range binary data mode bcd data mode bina~ bcd data mode data mode o seconds o-59 $w-s3b $w-$59 15 21 1 seconds alarm o-59 $00-$3b $w-$59 15 21 2 minutes o-59 $w-$3b $w-$59 3a 56 .! ,. a),,),, 3 minutes alarm o-59 $w-$3b $m-$59 3a 56 l.~:~ :. *l~\,\. ,,.l.,.,$.. , t,., ~ ,1. . . hours $01-$oc (am) and $01-$12 (am) and ~ *:~\ ,:::?~? ,<$,+ (12 hour mode) 1-12 $81 -$8c ( pm) 05 05 ~ ., ? ?~,z is,. $81-$92 (pm) ,1,, .y ,t,,,8t:i.,.. ~,~m,., .),,.: ,,, ~ 4 hours ,,,:s ~ ~. ,..v (24 hour mode) o-23 $co-$17 $w-$23 05 %$ ,?@: $, . . . . ,>., !? hours alarm 1-12 $01-$oc (am) and $01-$12 (ami and 05 (12 hour mode) $81-$8c (pm) $81-$92 (pm) ,:ft<+;:t?~ 5 ,. hours alarm %,... \\. !: o-23 $w-$17 $~-23 05 ~$+j >,, (24 hour mode) ?05 ,. $~?.. ?< i,) dav of the week !t. t$:i;~:;,, 6 sunday= 1 1-7 $01-$07 $01-$07 periodic interrupt selection the periodic interrupt allows the ~ pin to be triggered from once every 5w ms to once every 30.517 ps. the periodic interrupt is separate from the alarm interrupt which may be output from once per second to once per day. table 5 shows that the periodic interrupt rate is selected with the same register a bits which select the square-wave frequency. changing one also changes the other. but each function may be separately enabled so that a program could switch between the two features or use both. the sqw pin is enabled by the sqwe bit in register b. similarly the periodic interrupt is enabled by the pie bit in register b. periodic interrupt is usable by practically all real-time systems. it can be used to scan for all forms of inputs from contact closures to serial recieve bits or bytes. it can be used in multiplexing displays or with software counters to measure inputs, create output intervals, or await the next needed software function. update cycle the mc14~18a executes an update cycle once per second, assuming one of the proper time bases is in place, the dvo-dv2 divider is not clear, and the set bit in register b is clear. the set bit in the ?l? state permits the program to initialize the time and calendar bytes by stopping an ex- isting update and preventing a new one from occurring. the primary function of the update cycle is to increment the seconds byte, check for overflow, increment the minutes byte when appropriate and so forth through to the year of the century byte. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a ?don?t care? code (1 ixxxxxx) is present in all three positions. .! ~:)::. with a 4.19~ mhz or 1.048576 mhz time base thq$~~~+~$ date cycle takes 248 ps while a 32.708 khz time base~ ~~~ ,&*& cycle takes 1984 ps. during the update cycle, the t~~~?~en- dar, and alarm bytes are not accessible by the p~$~s~~ pro- gram. the mci%818a protects the progra~>~~% reading transitional data. this protection is provid~>~~switch ing the time, calendar, and alarm portion,~~*~~# ram off the microprocessor bus during the entir~ up~ate cycle. if the processor reads these ram loca,@%&w~ore the update is (,.:, complete, the output will be undefined. the update in pro- gress (uip) status bit is set during the interval. a program which randomly accesses the time and date in- formation finds data unavailable statistically once every 4032 attempts. three methods of accommodating nonavailability during update are usable by the program. in discussing the three methods, it is assumed that at random points user pro- grams are able to call a subroutine to obtain the time o$$gay. the first method of avoiding the update cycle, ~~,~$%e update-ended interrupt. if enabled, an interrupt @~@ks*after every update cycle which indicates that oveb;~w,;.&s are available to read valid time and date inforrn~~&$??buring this time a display could be updated or the i~fqw$$bn could be transferred to continuously availablq,t.&~~$,*before leaving the interrupt service routine, the ~~~~$ bit in register c should be cleared. ?~,>$;: ,4 .$,.? \.. the second method uses t$~wate-in-progress bit (u i p) in register a to determin~;ti~~~%~update cycle is in progress or not. the ui p bit will ,~j%,,$hce per second. statistically, the uip bit will indiq$~;~~~t time and date information is ? $+ unavailable once ~,~ery ?~~~ attempts. after the u i p bit goes high, the updat~$?~~~,begins 244 ps later. therefore, if a low is read on th~~l~$it, the user has at least 2~ ws before the time/cale@& d~ta will be changed. if a ?l? is read in the uip bit, {~~@$fie/calendar data may not be valid. the user shou~,d avb$~ interrupt service routines that would cause the ti~)~tieded to read valid time/calendar data to exceed ,p%;> <<,j~%$~#e third method uses a periodic interrupt to determine if %$s-j% update cycle is in progress. the uip bit in register a is set ???$ high between the setting of the pf bit in register c (see ,..:, ?,. figure 15), periodic interrupts that occur at a rate of greater than tbuc+tuc allow valid time and date information to be read at each occurrence of the periodic interrupt. the reads should be completed within (tpl + 2) + tbuc to ensure that data is not read during the update cycle. to properly setup the internal counters for daylight sav- ings time operation, the user must set the time at least two seconds before the rollover will occur. likewise, the time must be set at least two seconds before the end of the 29th or 30th day of the month. tpl = periodic interrupt time interval (500 ms, 250 ms, 125 ms, 62,5 ms, etc. per table 5) tuc = update cycle time (2w ps or lw ps) tbuc = delay time before update cycle (2m ks) m motorola semiconductor products inc. 14 registers the m c146818a has four registers which are accessible to the processor program. the four registers arealsofullyac- cessible during the update cycle. register a ($oa) msb ls b read/ write b7 b6 b5 b4 b3 b2 bl bo register uip dv2 dv1 dvo r s3 rs2 rs1 rso except uip uip ? the update in progress (uip) bit is a status flag that may be monitored by the program. when uip is a ?l?, the update cycle is in progress or will soon begin. when uip is a ?u?, the update cycle is not in progress and will not be for at least 244 ps (for all time bases). this is detailed in table 6. the time, calendar, and alarm information in ram is fully available to the program when the uip bit is zero ? it is not in transition. the uip bit is a read-only bit, and is not af- fected by reset. writing the set bit in register b to a ?l? inhibits any update cycle and then clears the uip status bit. table 6 ? update cycle times time base minimum time update cycle ~me before update uip bit (oscl) (tuc) cycle (tbuc) 1 4.lww mhz z@ ps ? 1 1.046576 mhz z& fls ? 1 32.766 khz lw~s ? o 4.194304 mhz ? 244 fis o 1.m576 mhz ? 244 ps o 32.766 khz ? 244 fis dv2, dvi, dvo ? three bits are used to permit the dro- gram to select various conditions of the 22-stage divider chain. the divider selection bits identify which of the thre:~ time-base frequencies is in use. table 4 shows that tj,ti?&j2, bases of 4.194304 mhz, 1.046576 mhz, and 32.7~ k~~)~~, ?? be used. the divider selection bits are also used to$,~j&~,j~& divider chain. when the time/calendar is first ini~~t~~:~~the program may start the divider at the precise,~~$~&red in the ram, when the divider reset is removed;~~~:~wt update cycle begins one-half second later. thes%.th~e read/write bits are not affected by reset. ~d??: >~- . . ;.i ..:.,\~, ~ ,{.,!$.~..$.. *.,.>*,,, rs3, rs2, rs1, rso ? the fo$~ ray selection bits select one of 15 tapes on the 22-sta~.~w~~&@p, or disable the divider output. the tap selected may ~.~hed to generate an output square wave (sqw pin) ~i~or &periodic interrupt. the pro- gram may do one of ~~~~wing: 1) enable the interrupt with. the pie bit, ~~~~~le the sqw output pin with the sqwe bit, 3) en@?~th at the same time at the same rate, or 4) enable n,g~w~~~?able 5 lists the periodic interrupt rates and the sqq~re-.g%ve frequencies that may be chosen with the rs ~j~%h@e four bits are readlwrite bits which are not affecte,~q~?%es et. ~ ,.,1, $,,,, .)e~,{., regl~ei b ($ob) msb lsb read/ write b71b61b51b41 b31b21bl bo register set i pie i aie ] uiei sqwei dm ] 24/12 i dse set ? when the set bit is a ?o?, the update cycle func- tions normally by advancing the counts once-per-second. when the set bit is written to a ?1?, any update cycle in 1? @ motorola progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. set is a read/write bit which is not modified by reset or internal functions of the MC146818A. pie ? the periodic interrupt enable (pie) bit is a read/write bit which allows the periodic-interrupt flag ( pf) bit in register c to cause the l~pin to be driven low. a pro- gram writes a ?1? to the pie bit in order to receive periodic interrupts at the rate specified by the rs3, rs2, rsi, and rso bits in register a, a zero in pie blocks l~q from being initiated by a periodic interrupt, but the periodic flag ( p~) bit is still set at the periodic rate. pie is not modified b~,a~&$~o- aie ? the alarm interrupt enable (al e) ~t$f&j&i$&ad/write bit which when set to a ?1? permits the @~rfl~~& (af) bit in register c to assert i rq. an alarm inte~~@?\$occurs for each second that the three time bytes e~~~~~~&i?hree alarm bytes (including a ?don?t care? alarm &od&tq~ binary 1 ixxxxx). when the aie bit is a ?u?, the ~~~jt does not initiate an ~q signal. the reset pin cle~f~~s~~% ?v?. the internal func- tions do not affect the ,~~,t~t~ uie ? the uie (q~~~~~%%ded interrupt enable) bit is a read/write bit which e?, ~7~s the updat%end flag (u f) bit in % register c to a@~,,lf the reset pin going low or the set bit goin~~~~~c~ears the u ie bit. .4, :$, . sqw~;~~&&n the square-wave enable (sqwe) bit is set to a ?l??k~~ the program, a square-wave signal at the fre- qu~~y spefified in the rate selection bits (rs3 to rso) ap- w$s @ the sqw pin. when the sqwe bit is set to a zero ,,,,, ~@e~qw pin is held low. the state of sqwe is cleared by ,,~,;~~~~?k es et pin. sqwe is a read/write bit. *$:=: ,.,:. +:,8 dm ? the data mode ( dm ) bit indicates whether time .1, ..,} and calendar updates are to use binary or bcd formats. the ?? dm bit is written by the processor program and maybe read by the program, but is not modified by any internal functions or reset. a ?l? in dm signifies binary data, while a ?u? in dm specifies binary-coded-decimal (bcd) data. 24/12 ? the 24/12 control bit establishes the format of the hours bytes as either the 24hour mode (a ?l?) or the 12-hour mode (a ?u?), this is a read/write bit, which is af- fected on iy by software. dse ? the daylight savings enable (dse) bit is a readlwrite bit which allows the program to enable two special updates (when dse is a ?1?). on the last sunday in april the time increments from 1:59:59 am to 3:00:00 am. on the last sunday in october when the time first reaches 1:59:59 am it changes to 1:00:00 am. these special updates do not occur when the dse bit is a ?jo?. dse is not changed by any internal operations or reset. register c ($oc) msb lsb read-only b7/b61b51b4 b3 b bl i bo register irqfipfiafiufioio joio irqf ? the interrupt request flag (irqf) is set to a ?l? when one or more of the following are true: pf=pie=?i? af=aie=?i? uf=uie=?i? i.e., irqf= pf*pie+ af*aie+uf*uie semiconductor products inc. 15 any time the irqf bit is a ?l?, the 1~ pin is driven low. all flag bits are cleared after register c is read by the pro- gram or when the reset pin is low. pf ? the periodic interrupt flag (pf) is a read-only bit which is set to a ?l? when a particular edge is detected on the selected tap of the divider chain. the rs3 to rso bits establish the periodic rate. pf is set to a ?l? independent of the state of the pie bit. pf being a ?l? initiates an ~ signal and sets the irqf bit when pie is also a ?l?. the pf bit is cleared by a reset or a software read of register c. af ? a ?l? in the af (alarm interrupt flag) bit indicates that the current time has matched the alarm time. a ?l? in the af causes the ~ pin to go low, and a ?l? to appear in the irqf bit, when the aie bit also is a ?1 .? a reset or a read of register c clears af. uf ? the update-ended interrupt flag (uf) bit is set after each update cycle. when the uie bit is a ?l?, the ?l? in uf causes the irqf bit to be a ?l?, asserting 1~. uf is cleared by a register c read or a reset. b3 to bo ? the unused bits of status register 1 are read as ?o?s?. they can not be written. register d ($od) msb lsb b7 b6 b5 b4 b3 b2 bl bo read only vrt o 0 0 0 0 0 0 register vrt ? the valid ram and time (vrt) bit indicates the condition of the contents of the ram, provided the power sense (ps) pin is satisfactorily connected. a ?o? appears in the vrt bit when the power-sense pin is low. the processor program can set the vrt bit when the time and calendar are initialized to indicate that the ram and time are valid. the vrt is a read only bit which is not modified by the res~t pin. the vrt bit can only be set by reading register q:~?~,, .,\, ., ~~:;,>,, b6 to bo ? the remaining bits of register d are unused. they cannot be written, but are always read as ?os. ? typical interfacing the MC146818A is best suited for use with microproces- sors which generate an address-then-data multiplexed bus. figures 16 and 17 show typical interfaces to bus-compatible processors. these interfaces assume that the address decoding can be done quickly. however, if standard metalgate cmos gates are used, the c?s setup time may be violated. figure 18 illustrates an alternative method o?s:$hip selection which will accommodate such slower dq~?~~&! the MC146818A can be interfaced to single#hj@.filcro- computers (mcu) by using eleven port lines@~~,@ubwn in figure 19. non-multiplexed bus micropro@~*&~an be in- terfaced with additional support. .*.$ ? ? {*({f ,<,,: .@$s there is one method of usin~.+~~~~@ultiplexed bus MC146818A with non-multiplexed *s ~pcessors. the inter- face uses available bus control ~ign?&#?to multiplex the ad- dress and data bus togetherik?~:~~~ an example using eitha~t~b:~~otorola m cwoo, mc6802, mcw08, or mc6809 ~~a&$r,~essor is shown in figure 20. when the mc14681~/&~,~mapped as shown in figures 19 and 20, the as and d\%,~inputs should be left in a low state when the part iqjf~}lbeing accessed. refer to the _ pin description j@~l\~ conditions which must be met before stby ca~, ~~ r,~ognized, figur~~:? fl!~ftrates the subroutines which maybe used for dat~jtrans%rs in a non-multiplexed system. the subroutines :h~u~.be entered with the registers containing the following ;&8f&; ?t: $q,f$:?@~&cumulator a: the address of the rtc to be accessed. ?~~~~> accumulator b: write: the data to be written. ~~..~t read: the data read from the rtc. .:!a l,- the rtc is mapped to two consecutive memory locations ? rtc and rtc+ 1 as shown in figure 20. figure ~@~~:*l&18a interfaced with motorola com,,@~~j@& multiplexed bus microprocessors * other h mc6801 > peripherals mc146b05e2 and memorv w + address decode* \ i ct ~q r/~ ds as ad@ad7 reset~ reset vdd MC146818A ckout ckfs stby sqw + 1 ??? ??? i i i i l high-speed silicon- gate cmos or ttl i address decoding i l?? ?_ ?__ ??, h @ motorola semiconductor products inc. 16 -?. i 8 address/data 8 address latch enable (ale~ / 8085 read ~) e + + other 8m wri?e (=) periph~@ls interrupt request ~ andw~y 8049 4 8/4 address address decode i m l~q r/~ ds as ~m~> figure 17 ? mc148818a interfaced with competitor compatible multipl~ed bus microprocessors ?:(,,, figure 18 ? mc cmos multiplexed microp~@~,sor with slow addressing decoding m c14@05e2 @ ti?$~~?exed address/data oscl i i ?? as riw irq ~~8a interface with mc148805w ado-ad7 i i i reset vdd ?1 mot ckout MC146818A ckfs stby sqw a 4 i ~_______-----___2l v ~d ei i i i this illustrates the use of cmos gating for address decoding. f 4. iw304 mhz (typ) @ motorola semiconductor products inc. 17 figure 19 ? mcl~18a interfaced with the ports of a typical single chip microcomputer m c3870 m c6805 mc 146805 s2000 8021 t i i i l ??? ? ?? 4. 193w mhz (tvp) a * note: c= can be controlled by a port pin (ifjav}#able). *. <$ do-d7 as stby ~ado-ad7 vss fl_ power failure circuit (see stby description) @ motorola semiconductor products inc. 18 ? .-? figure 21 ? subroutine for reading and writing the mcl@18a with a non-multiplied bus read sta rtc ldab rtc+ 1 rts write sta rtc stab rtc+ 1 rts b motorola semiconductor products inc. 19 package dimensions motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola and @are registered trademarks of motorola, inc. motorola, inc. is an equal employment opportunity/ affirmative action employer. m motorola semiconductor products inc. 3501 ed bluestein blvd., austin< texas 78721 . a subsidiary of motorola inc. |
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